There has been known a light coupled solid state relay including a light emitting element which emits lights according to an input signal; and a light receiving element which receives an optical signal from the light emitting element to produce an electromotive force. In the light coupled solid state relay, an output MOSFET (Metal Oxide Silicon Field Effect Transistor) is turned on and off by using the electromotive force. The solid state relay has been employed for various uses since it has a small On-resistance and a small volume and can control a fine analog signal.
The solid state relay includes a light emitting element, such as an LED, which generates an optical signal in response to an input signal; a photodiode array which receives the optical signal and produces an electromotive force; a photoelectric conversion unit including a charge and discharge circuit which charges and discharges the produced electromotive force; and an output element including a MOSFET which performs connection and disconnection according to a voltage from the charge and discharge circuit.
As for such a MOSFET, a SiC-MOSFET made of SiC has drawn attention thanks to its high withstand voltage and small On-resistance. In this regards, a power transistor where a plurality of transistor cells are arranged in an active area included in a SiC substrate has been in the mainstream. However, it is difficult to increase the withstand voltage due to the breakdown caused by the electric field concentration generated around the transistor cells.
Accordingly, various ideas have been suggested. As one of them, there is disclosed a MOSFET in which a floating ring is formed by introducing a first conductive impurity into an annular portion located at the periphery of an active area (see, e.g., Japanese Patent Application Publication No. 2006-344802).
In a solid state relay disclosed in the above-cited reference, as shown in FIG. 9, an active area 111 serving as a FET (Field Effect Transistor) is formed on a SiC semiconductor substrate 101. An inner ring 116 is disposed at a peripheral portion of the active area 111, the potential of the inner ring 116 being fixed to a same level as the potential of a source electrode 108. Further, an electrically floating ring 112 is disposed to be separated from the inner ring 116 with a predetermined interval therebetween. Furthermore, an outer ring 113 serving as a drain region is disposed at a peripheral portion of the SiC semiconductor substrate 101, the potential of the outer ring 113 being fixed to a same level as the potential of the SiC semiconductor substrate 101.
Specifically, in the solid state relay disclosed in Japanese Patent Application Publication No. 2006-344802, the inner ring 116 is provided at an outermost peripheral portion of the active area 111 serving as a FET, and connected to the source electrode 108 via a contact 117. Then, the uniformity and stability of an electric field distribution in the vicinity of the active area 111 are obtained by fixing the potentials of the inner ring 116 and the outer ring 113 to same levels as those of the source region 104 and a drain, respectively.
Further, the floating ring 112 is disposed outside the inner ring 116. A depletion layer 130 is formed to extend from a p type wall and the inner ring 116 toward the outer ring 113 farther than the floating ring 112, which does not form a sharp curve (reference numeral “130A” indicates a depletion layer in the case of providing no floating ring 112). Accordingly, it is possible to effectively release the electric field concentration.
However, in the above-referenced solid state relay, there is a problem in that, when a high voltage is applied between the drain and a source, a leak current via a first conductive region is increased since the inner ring 116 is provided at the outermost peripheral portion of the active area serving as a FET and has the same potential as that of the source region 104. Accordingly, it is required to prepare measures. Further, it is necessary to provide the inner ring 116 and the floating ring 112 as well as the outer ring 113. This causes an increase in the element area.